Digital Signal Processing Reference
In-Depth Information
R1
Z
oo
DO
+
RI
+
+
−
R2
DO
−
RI
−
Z
oo
R1
(a)
Z
oo
C1
DO
+
RI
+
R1
R2
+
−
V
tt
R1
DO
−
RI
−
C1
Z
oo
(b)
Figure 13.11
(a) Termination scheme when the even and odd modes cannot be ignored. (b) By
connecting
R
1 to
V
tt
the line is simultaneously rebiased and terminated. Capacitor
C
1 allows the
transmitter and receiver to operate at different bias voltages.
RZ
=
(13.4)
1
oe
2
ZZ
R
=
oe
oo
2
ZZ
−
(13.5)
oe
oo
Figure 13.11(b) shows how capacitors and a power supply can be used to
simultaneously rebias and terminate a diff-pair. The ability to both
level shift
and
terminate is useful when the receiver and transmitter common-mode voltages are
different. For instance, this technique is used when it is necessary to send signals
between logic families operating at different supply voltages. In this case
V
tt
is set to
the common-mode voltage required by the receiver and so puts the diff-amp at the
optimum bias point for its operation. The transmitter can be signaling at a voltage
significantly different from
V
tt
, but the capacitors only allow the signal amplitude
