Digital Signal Processing Reference
In-Depth Information
It is evident from Figure 12.12(a) that when the line is series terminated, a
plateau voltage is created at each load as the incident wave passes by. In this case,
the plateau is not quite equal to half the value of
V
dd
, the power supply feeding the
driver.
In general, if the plateau voltage is greater than the receiver switching thresh-
old, the receivers will detect the voltage as a valid logic level and will switch on the
incident wave. However, incident wave switching is not occurring in this particular
case because the plateau voltage does not exceed the receiver switch point.
Instead, each of the loads must wait until the reflection created at the open cir-
cuit at the very end of the line arrives and increases the plateau to a higher voltage.
Since the reflection is created at the furthest load,
C
L
3
is the first to switch. We can
see in Figure 12.12 how each of the remaining loads switch in reverse order as the
reflection travels from
C
L
3
toward
C
L
1
.
In contrast, the response when parallel terminated [appearing in Figure
12.12(b)] shows that there is no plateau and reflections are not required for the
signal to reach the switch point. In this case, the load closest to the driver (
C
L
1
)
switches before
C
L
3
.
Although the parallel termination dissipates more power (including power in
the driver), it gives the fastest overall response because the signal is high enough
to exceed the receiver's switch point as it first passes by rather than having to wait
for the reflection.
This timing difference is evident in Figure 12.12. For instance, if we use 2.4V
as the receiver switch point, we can see that in this example load
C
L
1
reaches that
voltage at a time of about 1.2 ns when parallel-terminated and at roughly 5.7 ns
when series-terminated. However, the load
C
L
3
reaches 3.4 ns for both the series
and parallel termination schemes.
12.7.2 Response When Signal Rise Time Is Comparable to the Transmission
Line Delays
In Chapter 6 we saw that if the line was longer than half the signal rise time, the line
components acted as distributed elements. We can look at this in the reverse and
say that if the signal rise time is longer than twice the electrical length of the line
than the elements appear as a single lump. For instance, a transmission line having
a 0.5-ns electrical length would appear as a single RLC lump if the signal rise time
was 1 ns, but it would appear more as a distributed circuit if the rise time was less
(such as 750 ps).
We will use this insight to analyze the effects of loads evenly distributed along
a transmission line when the rise time is comparable to the electrical length of the
line.
A driver source series terminated to a 12 inch (30.5 cm) 65
transmission line
is shown in Figure 12.13. Without loads the total one way delay of this line is 2.1
ns. A receiver (represented by load capacitors
C
L
1
and
C
L
2
) are placed midway and
at the end of the line. A 65
Ω
Ω
resistor
R
s
is used to impedance match the driver to
the transmission line.
A 3.3-V driver with an on resistance much lower than 65
launches a fast rise
time signal down the transmission line. The dotted curve in Figure 12.14 shows
that the voltage
V
ne
has an initial plateau of 1.65V. Since this is one half of the
Ω
