Digital Signal Processing Reference
In-Depth Information
CHAPTER 12
Termination Strategies
12.1 Introduction
In the previous chapters we implied that the load and transmission line imped-
ances must match for proper electrical operation of an interconnect. However, the
actual goal is to ensure that the received signal crosses the receiver threshold with
adequate timing margin and, at least for clocks, that the signal transitions smoothly.
The signal integrity engineer accomplishes this by arraigning the wiring topol-
ogy and selecting the termination scheme and I/O drivers so that reflections do
not cause multiple pulses, glitches in the waveform, or unacceptable voltage levels.
Terminations can be placed at the load end (far-end termination) or at the driving
(source termination) end. The choice depends on available timing margins, the
wiring topology, the number of loads on a net and their location compared to one
another, and power dissipation.
12.2
Source Series Termination
Source series termination uses a resistance to connect the driver (the source) to the
transmission line. This resistance raises the impedance of the transmitter (TX in Fig-
ure 12.1) and is either a discrete resistor placed on the circuit board (shown as
R
s
),
or it is an integral part of the integrated circuit I/O cell. In some integrated circuits
the built-in series impedance can be selected (programmed) from a range of values.
12.2.1 Selecting the Resistance Value
Until now, we have tacitly assumed that the driver impedance has the same value
as the transmission line impedance. However, in some circumstances it can be ad-
vantageous for the driver impedance not to equal the transmission line impedance.
Three cases are shown in Figure 12.2 for the point-to-point configuration
shown in Figure 12.1. The driver impedance is very low so that series resistor
R
s
sets the total impedance value.
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