Digital Signal Processing Reference
In-Depth Information
References
[1]
Young, B., Digital Signal Integrity , Upper Saddle River, NJ: Prentice-Hall, 2001.
[2]
DeFalco, J. A., “Refl ections and Crosstalk in Logic Interconnections,” IEEE Spectrum , July
1970, pp. 44-50.
[3]
Paul, C. R., Analysis of Multiconductor Transmission Lines , New York: John Wiley &
Sons, 1994.
[4]
Hart, B. L., Digital Signal Transmission Line Circuit Technology , Oxford, U.K.: Van Nos-
trand Reinhold, 1988.
[5]
Rosenstark, S., Transmission Lines in Computer Engineering , New York: McGraw-Hill,
1994.
[6]
Catt, I., “Crosstalk (Noise) in Digital Systems,” IEEE Transactions on Electronic Comput-
ers , Vol. EC-16, No. 6, December 1967, pp. 743-763.
[7]
Thierauf, S. C., High-Speed Circuit Board Signal Integrity , Norwood, MA: Artech House,
2004.
[8]
Feller, A., et al., “Crosstalk and Refl ections in High-Speed Digital Systems,” Proceedings of
the Fall Joint Computer Conference , Washington, D.C., December 1965, pp. 511-515.
[9]
Sengupta, M., et al., “Crosstalk Driven Routing Advice,” Proceedings of the 44th Elec-
tronic Components and Technology Conference , Washington, D.C., May 1994, pp.
687-694.
[10]
Shi, W., “Evaluation of Closed-Form Crosstalk Models of Coupled Transmission Lines,”
IEEE Transactions on Advanced Computing , Vol. 22, No. 2, May 1999.
[11]
Polar Si9000 Field Solver, version V9.01.00, Polar Instruments, Inc. Beaverton, OR.
[12]
Djordjevic, A. R., et al., LINPAR for Windows , Norwood, MA: Artech House, 1999.
[13]
SmartSpice, Simucad Design Automation, Version V3.10.8.R, Santa Clara, CA.
[14]
Ladd, D. N., et al., “SPICE Simulation Used to Characterize the Cross-Talk Reduction Ef-
fect of Additional Tracks Grounded with Vias on Printed Circuit Boards,” IEEE Transac-
tions on Circuits and Systems II: Analog and Digital Signal Processing , Vol. 39, No. 6, June
1992.
[15]
Bakoglu, H. B., Circuits, Interconnections, and Packaging for VLSI , Reading, MA: Addi-
son-Wesley, 1990.
[16]
Suntives, A., et al., “Using Via Fences for Crosstalk Reduction in PCB Circuits,” 2006
IEEE International Symposium on Electromagnetic Compatibility , Portland, OR, Vol. 1,
August 1-18, 2006, pp. 34-37.
 
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