Digital Signal Processing Reference
In-Depth Information
3.1V
3V
2.9V
2V
1V
0V
0.0s
5.0 ns
10.0 ns
15.0 ns
20.0 ns
Figure 9.10
Launched voltage is lower when the signals are out of phase (dotted curve) than when
in phase (solid curve).
3V
2V
650 ps
1V
0V
0.0s
5.0 ns
10.0 ns
15.0 ns
20.0 ns
Figure 9.11
Victim receiver responds sooner when the traces switch out of phases (dotted curve)
than when they are in phase (solid curve).
behavior is characteristic of CMOS I/O drivers and is independent of any parasitic
inductance in the power or signal leads.
