Digital Signal Processing Reference
In-Depth Information
9.4
What Effect Does Coupling Have on Impedance and Delay?
The circuit setup shown in Figure 9.5 shows four aggressor microstrip traces (A4
through A1) surrounding a victim (V) microstrip. They are designed to have an
impedance of 50
, and are driven from ASIC 1 with identical I/O drivers.
By systematically switching each aggressor in or out of phase with the victim
trace, we can determine how the mutual capacitance and inductance affect the
victim impedance and delay for each switching mode. This is shown in Table 9.1,
where a “
Ω
”
means the signals swing in opposite directions. A signal that does not switch (is
static) is shown with an S.
Evidently, even though the traces are designed to be 50
+
” indicates that the signal transition is in the same direction, while a “
−
, they only have that
value when their neighbors are static. The impedance is lowest when all of the
aggressors are out of phase with the victim, and it is highest when they are all in
phase.
The switching activity also affects the microstrip (but not stripline) propaga-
tion time. Microstrip delay is shortest when the signals are all out of phase, and it
is the longest when they are all in phase. As we saw in Chapter 7, stripline propaga-
tion delay is determined by the dielectric constant, which is why it is the same for
all switching modes and so is not shown in Table 9.1.
However, data-dependent timing jitter will occur at the output of receivers con-
nected to either stripline or microstrip traces. This behavior is a property of the cir-
cuit rather than the transmission line and is an artifact of the changing impedance
Ω
ASIC 2
A
S
IC
1
1m
A4
tpd
A3
5 mils
V
5 mils
A2
A1
Figure 9.5
Top view of four aggressor microstrip traces surrounding a victim trace connecting ASIC
1 to ASIC 2 and driven by identical drivers.
