Hardware Reference
In-Depth Information
Sequence
FDL(S-FDL)
Verified
S-FDL
Sequence
Object
Linked
object
Thread
FDL(T-FDL)
Verified
T-FDL
Thread
Object
Fig. 3.55
Toolchain of FE-GA software development
3. Transfer data.
An outside CPU or a DMA controller transfers necessary data for operation from
an outside buffer memory or another bank of the FE-GA's local memory to the
specified bank of the local memory. It also transfers the operation result to memo-
ries inside and outside the FE-GA.
4. Thread switch (recon fi guration).
After completion of the setups, an outside CPU triggers the FE-GA, and FE-GA
starts its operation by the sequence manager. The sequence manager observes both
the internal state and trigger events that establish the condition for thread switching.
When the condition for thread switching is satisfied, it updates the internal state and
executes thread switching. Thread switching consumes two cycles. When the pro-
cessing is finished or an error occurs, it halts the processing and issues an interruption
to an outside CPU for service.
5. Execute operations.
When thread switching is completed, it starts the processing defined with
con fi gurations identi fi ed by the next-switching logical thread number. The processing
is continued until the next thread-switch condition is satisfied.
3.2.6
Software Development Environment
The programming of the FE-GA involves mapping the operation cell array called a
thread and a sequence of multiple threads as depicted in Fig.
3.52
. The FE-GA has
a dedicated assembly-like programming language called Flexible-Engine Description
Language, or FDL. There are two types of FDLs; one is Thread-FDL (T-FDL),
which describes a cell-array mapping, and the other is Sequence-FDL (S-FDL), which
describes a sequence of threads. Users first create both T-FDL and S-FDL with an
FE-GA editor and convert them into binary using FE-GA tools as shown in Fig.
3.55
.
The tool-chain includes an editor, a constraint checker, an assembler, and a linker.
The editor is a graphical tool on which users set up functions of each operation cell,
data allocation of the local memory, and sequence de fi nition of threads. It has a simu-
lator so as to verify users' FE-GA programming, and it can also generate FDLs.
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