Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 81

Start

Set up configuration
control registers

Set up sequence
control registers

Transfer data

Thread switch?

Operation
finished?

Execute operations

Thread switching Transfer data

End

Fig. 3.54 Operation fl owchart of FE-GA

3.2.5 Operation Flow of FE-GA

The FE-GA carries out various processes on a single hardware platform by setting
up configurations of the operation cell array, the LS cells, and the crossbar network
and by changing the configurations dynamically. Figure 3.54 shows an operation
flowchart of an FE-GA.
The operation steps of the FE-GA are as follows:

1. Set up con fi guration control registers.
The FE-GA executes specified arithmetic processing in such a way that each cell
and the crossbar operates according to their configurations corresponding to CPU
commands. This specified processing is called a thread, which is identified by the
logical thread number. At this stage, an outside CPU or a DMA controller sets up
controlling resources in the configuration manager, such as registers that define buf-
fers storing configuration data and correspondence of a logical thread number to
data stored on the configuration buffer.

2. Set up sequence control registers.
The FE-GA provides states by combining the configuration state of each cell and
the crossbar identified by the logical thread number and parameters such as an oper-
ation mode and an operation state. A transition from a specified internal state to
another internal state is called a thread switch, and a series of switchings is called a
sequence. At this stage, an outside CPU or a DMA controller sets up a sequence
control table defining switching conditions and states before and after the switching
and initializes the internal state.