Hardware Reference
In-Depth Information
Fig. 3.48 Example of system
con fi guration incorporating
FE-GAs
DMA
controller
Interruption
controller
CPU
CPU
System bus
Memory
FE-GA
FE-GA
Peripherals
The features of the FE-GA are as follows. It has:
A 2D, nonuniform array structure formed with different types of operation cells
(24 ALU cells and 8 MLT cells) whose functions and connections are change-
able in a cycle
Simplified data transfer between four neighboring cells, therefore achieving
shortened wiring and high frequency
Flexible memory addressing using dedicated memory-access cells (10 LS cells)
A middle-capacity, multiple bank/port LM for temporary-operation data storage
(maximum of 16 KB × 10 banks and 2 ports)
A wideband XB network enabling flexible connection between the operation cell
array and the LS cells
A configuration manager (CFGM) that supports hierarchical-configuration data
management and background data transfer, which can be performed in parallel to
cell-array operation
A sequence manager (SEQM) supporting autonomous sequence control and
attainment of a highly independent subsystem
An interruption and dynamic memory access (DMA) transfer request feature to
control handover and synchronized data transfer for collaborative processing
with a CPU or DMA controller (DMAC) outside the FE-GA
Input/output ports handling streaming data with no impact on the system bus and
scalable increase in performance by multiple cascading FE-GAs based on a
remote memory-access feature
The FE-GAs are attached to the system bus usually connected to the CPUs, a
DMA controller, an interruption controller, peripherals, and a memory as illustrated
in Fig. 3.48 . The CPUs control the FE-GAs and the DMA controller and execute
program parts that are not suitable for processing on the FE-GAs. The FE-GAs
execute processes previously accelerated by dedicated special logic circuits. Today's
applications for SoCs (systems on a chip) that incorporate CPUs and accelerators
demand more complicated functions. However, due to limitations in area, power
dissipation, and development cost, no existing SoCs have sufficient space to mount
the increasing numbers of special logics. The FE-GAs can execute multiple opera-
tions that are not necessarily executed simultaneously by switching their functions.
This makes it possible to save the area size of such SoCs and to use the space
ef fi ciently.
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