Hardware Reference
In-Depth Information
Conventional SH-3E Architecture
FMUL
FMAC
FDIV
FMOV
142
FMOV
FMUL
FMAC
FSQRT
FDIV
SH-3E ISA, Superscalar, SRT FDIV/FSQRT
FMUL
FMAC
FDIV
FMUL
FMAC
FSQRT
FDIV
SH-4 ISA (with FIPR, FTRV), Out-of-order FDVI/FSQRT
FMUL
FTRV
FDIV
FSQRT
FIPR
Coordinate & Perspective
Transformations
Intensity Calculation
52% shorter
FMUL
Arithmetic
49% shorter
SH-4
SH-X
FDIV
FSQRT
FDIV
FDIV
FSQRT
FDIV
30% longer
33% longer
SH-X ISA (with FSRRA)
FSRRA
FIPR
FTRV
FMUL
FMUL
51% shorter
Arithmetic
45% shorter
0
11
19
20
26
39
40
52
60
68
74
80 81
Resource-occupying cycles
Fig. 3.39 Resource-occupying cycles of SH-3E, SH-4, and SH-X for a 3D benchmark
1.0
1.0
1.0
0.5
µ
m
SH-3E
0.25
µ
m
5.1
2.7
1.9
SH-4
x 2.4
0.18
m
µ
5.1
1.9
2.7
0.13
µ
m
SH-X
13
2.0
6.5
0
4
8
12
0
1
2
0
2
4
6
Architectural
Performance
Relative
FPU area
Architectural
area performance ratio
0.97
7.0
0.14
SH-3E
0.5
µ
m
0.25
µ
m
10
8.0
1.3
SH-4
x 5.8
0.18
µ
m
12
3.0
4.0
0.13
µ
m
SH-X
36
1.6
23
0 0 0 0 02468
0
10
20
Performance
(M polygons/s)
FPU area
(mm 2 )
Area performance ratio
(M polygons/s/mm 2 )
Fig. 3.40
Area ef fi ciencies of SH-3E, SH-4, and SH-X
area-performance ratio to compare the area efficiencies with no process porting
effect. Although the relative areas increased, the performance improvements were
much higher, and the efficiency was greatly enhanced. The lower half shows real
performance, area, and area-performance ratio. The efficiency was further enhanced
using the finer process. Similarly, the power efficiency was also enhanced greatly as
shown in Fig. 3.41 .
 
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