Hardware Reference
In-Depth Information
Mantissa (53 bits)
Higher (21 bits)
Lower (32 bits)
Lower x Lower (64 bits)
+
Lower x Higher (53 bits)
=
+
Higher x Lower (53 bits)
=
+
Higher x Higher (42 bits)
=
Product (53 bits + guard/round bits)
Sticky bit
Fig. 3.26
Double-precision FMUL emulation
Mantissa (53 bits)
Higher (21 bits)
Lower (32 bits)
Less Lower Alignment Range (66 bits)
Less Lower
OR
Less Higher Alignment Range (76 bits)
Less Higher
+
Greater Lower
=
+
Sticky bit
Greater Higher
=
Sum (53 bits + guard/round bits)
Fig. 3.27
Double-precision FADD/FSUB emulation
instruction as well as 24-bit multiplication and 73-bit addition for the FMAC.
The 73 bits are necessary to align the added to the product even when the exponent
of the addend is larger than the product. Then the FPU supports 32-bit multiplica-
tion and 73-bit addition. The 53-bit input mantissas are divided into higher 21 bits
and lower 32 bits for the emulation. Figure 3.26 illustrates the FMUL emulation.
Four products of lower-by-lower, lower-by-higher, higher-by-lower, and higher-by-
higher are calculated and accumulated properly. FPU exception checking is done at
the first step, the calculation is done at second to fifth steps, and the lower and
higher parts are outputted at fifth and last steps, respectively.
Figure 3.27 illustrates the FADD and FSUB emulation. The less operand is
aligned to the greater operand by comparing which is larger at the first step as well
as checking the exception. Only higher halves of the input operands are compared
 
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