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performance of 25 MIPS in 500 mW by optimization on the redesign from the SH-1.
The SH-2 integrated a cache memory and an SDRAM controller instead of the
ROM and the RAM of the SH-1. It was designed for the systems using external
memories. The integrated SDRAM controller was not popular at that time, but
enabled to eliminate an external circuitry and contributed to system cost reduction.
In addition, the SH-2 integrated a 32-bit multiplier and a divider to accelerate mul-
timedia processing. And it was equipped to a home game console which was one of
the most popular digital appliances. The SH-2 extend the application field of the SH
processors to the digital appliances with multimedia processing.
The third-generation product SH-3 was manufactured using a 0.5-mm process in
1995 [ 7 ]. It operated at 60 MHz and achieved performance of 60 MIPS in 500 mW.
Its power efficiency was improved for a mobile device. For example, the clock
power was reduced by dividing the chip into plural clock regions and operating each
region with the most suitable clock frequency. In addition, the SH-3 integrated a
memory management unit (MMU) for such devices as a personal organizer and a
handheld PC. The MMU is necessary for a general-purpose operating system (OS)
that enables various application programs to run on the system.
The fourth-generation product SH-4 was manufactured using a 0.25-m m process
in 1997 [ 8- 10 ]. It operated at 200 MHz and achieved performance of 360 MIPS in
900 mW. The SH-4 was ported to a 0.18-mm process, and its power efficiency was
further improved. The power efficiency and the product of performance and the
efficiency reached to 400 MIPS/W and 0.14 GIPS 2 /W, respectively, which were
among the best values at that time. The product roughly indicates the attained degree
of the design, because there is a trade-off relationship between performance and
efficiency. The design is discussed in Sects. 3.1.2 and 3.1.5 .
The fifth-generation processor SH-5 was developed with a newly defined instruc-
tion set architecture (ISA) in 2001 [ 11- 13 ], and an SH-4A, the advanced version of
the SH-4, was also developed with keeping the ISA compatibility in 2003. The
compatibility was important, and the SH-4A was used for various products. The
SH-5 and the SH-4A were developed as a CPU core connected to other various
hardware intellectual properties (HW-IPs) on the same chip with a SuperHyway
standard internal bus. This approach was available using the fine process of 0.13 m m
and enabled to integrate more functions on a chip, such as a video codec, 3D graph-
ics, and global positioning systems (GPS).
An SH-X, the first generation of the SH-4A processor core series, achieved
performance of 720 MIPS with 250 mW using a 0.13-m m process [ 14- 18 ] . The
power efficiency and the product of performance and the efficiency reached to
2,880 MIPS/W and 2.1 GIPS 2 /W, respectively, which were among the best values
at that time. The low-power version achieved performance of 360 MIPS and
power efficiency of 4,500 MIPS/W [ 19- 21 ]. The design is discussed in Sects. 3.1.3
and 3.1.6 .
An SH-X2, the second-generation core, achieved performance of 1,440
MIPS using a 90-nm process, and the low-power version achieved power
efficiency of 6,000 MIPS/W [ 22- 24 ]. Then it was integrated on product chips
[ 25- 28 ]. The design is discussed in Sect. 3.1.4 .
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