Heterogeneous Multicore Architecture - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 17

References
1. Uchiyama K (2008) Power-efficient heterogeneous parallelism for digital convergence, digest of
technical papers of 2008 Symposium of VLSI circuits, Honolulu, USA, pp 6-9
2.Uchiyama K (2010) Power-efficient heterogeneous multicore for digital convergence,
Proceedings of 10th International Forum on Embedded MPSoC and Multicore, Gifu, Japan,
pp 339-356
3. Yuyama Y, et al (2010) A 45 nm 37.3GOPS/W heterogeneous multi-core SoC, ISSCC Dig:
100-101
4. Nito T, et al (2010) A 45 nm heterogeneous multi-core SoC supporting an over 32-bits physical
address space for digital appliance, COOL Chips XIII Proceedings, Session XI, no. 1
5. Arakawa F (2011) Low power multicore for embedded systems, CMOS Emerging Technology
2011, Session 5B, no. 1