Application Programs and Systems - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 193

RP-1

CPU
#0

CPU
#1

CPU
#2

CPU
#3

On-chip Interconnect

DRAM
Controller

Display
Unit
(DU)

Video
encoder

CPU #0

CPU #1 CPU #0 CPU #1

Frame
buffer
Plane 0

CPU #2 CPU #3 CPU #2

CPU #3

Display

DRAM

Fig. 6.21 RP-1 application system diagram

Penguin drawing 0
Penguin drawing 1

DU
initialization

Background
painting

application

…

Penguin drawing N

OS SMP Linux

UART LAN DU

driver

Memory (DRAM)

hardware

CPU #0 CPU #1 CPU #2 CPU #3

Fig. 6.22 RP-1 application software architecture

CPU #0 CPU #1

CPU #2 CPU #3

Fig. 6.23 Depiction of
penguin process in CPU #3

0