Application Programs and Systems - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 189

1 Frame Processing

Vector
Extraction

Vector
Extraction

Vector
Extraction

MX
Core

Object MAP
Creation

Object MAP
Creation

Object MAP
Creation

CPU#0

Event
Detection

Event
Detection

Event
Detection

CPU#1

Traffic situation
EX.) Run, Congestion

0 1 2 3 4 Time

Fig. 6.17 Frame pipelining scheme

Absolute difference
(each pixel)

SAD
value

Summation

Image Data
(8x8pixel)

Template Data
(8x8pixel)

Expression :

Fig. 6.18 Overview of SAD calculation

The absolute difference of each paired pixel between the two pixel blocks is first
determined and then their sum is calculated.
Figure 6.19 shows the implementation overview of SAD to the MX core. The
absolute difference between the sequential frames is processed line by line with the
PEs of the MX core in parallel. The MX core has a powerful data network between
PEs; therefore, inter-PE operations such as the summation are also easily imple-
mented. With these implementation techniques, effective and high-performance
SAD operations are realized with the MX core.
The performance evaluation of the S-T MRF application using the proposed SoC
architecture is illustrated in Fig. 6.20 . This graph shows the speed performance; the results