Hardware Reference
In-Depth Information
partition, the hypervisor traps every hardware resource access request that the
operating system and applications generate, in order to check their authenticity and
to provide the requested resource services if authorized.
Optimizing hardware utilization is one of the main goals of logical partitioning.
To achieve this goal, logical partitioning sacrifices the partition's physical isolation
in exchange for greater flexibility in dynamically allocating resources to partitions.
It also imposes performance penalties because the hypervisor is implemented in
software layers.
Our Approach
In terms of hardware design simplicity, implementing the partition controller for
physical partitioning of embedded processors involves a small amount of memory
and a simple logical circuit and does not require any architectural changes to the
CPU core. However, to mitigate logical partitioning's original virtualization perfor-
mance overhead, logical partitioning imposes several challenges on the CPU core
architecture, such as introducing a new execution mode on the CPU core [ 17 ] .
In terms of the simplicity of software development, physical partitioning
requires a new error-handling routine for the partition controller that can be imple-
mented as a simple interrupt handler in embedded systems and does not require the
modification of guest operating systems. However, logical partitioning requires a
hypervisor to arbitrate accesses to the underlying physical hardware resources so
that multiple guest operating systems can share them. Its paravirtualization
approach improves virtualization performance but requires modification of the
guest operating systems [ 18 ] .
In typical multidomain embedded systems, each domain's CPU, memory area,
and peripheral devices are physically different, and physical isolation and low over-
head are more important than partitioning flexibility. Therefore, we based our domain
partitioning on physical partitioning techniques and used the PPC hardware module
to implement physical isolation with low overhead.
Multicore Processor with Domain-Partitioning Mechanism
Figure 5.10 is a block diagram of the multicore processor we used to implement the
proposed domain-partitioning technique. The processor is a multicore chip contain-
ing four SH-4A processor cores, each of which is a 32-bit RISC microprocessor
containing an instruction cache, data cache in write-back mode, and memory man-
agement unit (MMU) with a translation look-aside buffer (TLB), which supports a
32-bit virtual address space. The SH-4A cores maintain consistency between data
caches and share instruction/data unified L2 cache in write-through mode. The pro-
cessor incorporates a DDR3-SDRAM memory controller (DBSC), local bus state
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