Software Environments - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 155

Table 5.7 Number of CPU instructions to implement atomic add
Number of CPU instructions

Using TAS instruction 16

Using LL/SC instruction 4

5.1.1.4 Considerations

As described before, the LL/SC instructions do not lock the bus. On the other hand,
the TAS instruction locks the bus and causes huge overhead. Moreover, atomic oper-
ation using the TAS instruction requires complex implementation because the TAS
instruction only compares binary data (zero or nonzero). For example, the number of
CPU instructions to implement an atomic add operation is shown in Table 5.7 .
The atomic add using TAS requires four times the number of CPU instructions com-
pared with LL/SC. This is also the case with other atomic operations. LMBench
results show this overhead. The advantage of LL/SC compared to TAS increases with
the number of atomic operations used in the benchmark [ 3 ] .

5.1.2 Power-Saving Features

5.1.2.1 Introduction

RP-2 is the multicore chip which has the following enhanced power-saving features:

￿ Power on/off control to each core

￿ Frequency control to each core

￿ Voltage control of the chip

Linux already has the power-saving frameworks CPU hot-plug and CPUfreq for
multicore processors [ 4, 5 ], but these frameworks have the following problems:

￿ No coordination between CPU hot-plug and CPUfreq

￿ CPUfreq has some governors that control voltage and frequency dynamically

according to system loads. However, CPU hot-plug does not have such a feature.
No coordination between voltage control and core frequency control ￿

￿ The input voltage to the chip limits the maximum frequency for CPU cores of

RP-2. This means each CPU core frequency is to be coordinately controlled with
the input voltage. However, CPUfreq governor does not have such a feature.

To resolve these issues, we have developed a new power-saving framework called
“ idle reduction ” based on CPU hot-plug and CPUfreq.

5.1.2.2 Implementation

Figure 5.1 and Table 5.8 show the structure of the idle reduction framework.