Hardware Reference
In-Depth Information
Table 5.1
Atomic operations of Linux
Operation type
Details
Spinlock
Lock operation using busy loop
Read/write lock
Lock operation for read/write access
Bit operation
Atomic operation for bit set and clear of variable
Add/declare operation
Atomic operation for increment/decrement of variable
Compare/exchange operation
Atomic operation for compare and exchange of two values
To port SMP Linux to new processor architecture, it is necessary to implement the
architecture-dependent part related to SMP. The number of source lines of the architec-
ture-dependent part related SMP is about 5 K lines in Linux version 2.6.16. Major parts
to be implemented are as follows [
1
] :
Boot sequence
Timer functions
CPU cache controls
TLB (translation look-aside buffer) controls
Inter-core communications
Atomic operations
Atomic operations are key primitives to support an SMP-type operating system.
They enable exclusive access to shared hardware resources such as memories and
I/O devices. They also strongly affect SMP performance. Therefore, we mainly
describe the implementation and evaluation of atomic operations.
SMP Linux uses the atomic operations described in Table
5.1
.
In the conventional Linux for a single CPU, all atomic operations are realized by
disabling interrupts to the CPU core. However, SMP Linux cannot use this method.
For example, while one CPU core disables interrupts for exclusive access to shared
objects, other CPU cores continue to run and touch them. To avoid such illegal
access, SMP Linux must use special CPU instructions to ensure atomic access
among CPU cores.
RP-1 has two types of CPU instructions for atomic operations: one is TAS (test-
and-set) instruction and the others are LL/SC (load-linked/store-conditional)
instructions. TAS instruction is used in a thread library in the conventional Linux for
a single CPU. LL/SC instructions are newly added to RP-1 to support an SMP-type
operating system:
1. TAS instruction.
The TAS instruction reads the data indicated by the address and sets the T-bit in
the status register to 1 if that datum is zero, or clears the T-bit to 0 if that datum is
nonzero. The instruction then sets bit 7 of the data to 1 and writes to the same
address. The bus is not released during this period.
2. LL/SC instructions.
The LL instruction is used in combination with an SC instruction to realize an
atomic read-modify-write operation. This instruction sets the LL/SC private flag to
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