Chip Implementations - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 144

SH - X4
SH - X4
SH - X4
SH - X4
CPU

SH - X4
SH - X4
SH - X4
SH - X4
CPU

SNC
L2
PWC

SNC
L2
PWC

CRU FPU CRU FPU

I$ DTU D$ I$ DTU D$

SH-X4
Cluster#0

SH-X4
Cluster#1

ILM UM DLM ILM UM DLM

SuperHyway-0 SuperHyway-1

FE
FE
FE
FE
LM

MX-2
MX-2
LM

SuperHyway-2 VPU5

Video
Processing
Unit

LBSC SPU2

Media
IPs

PCIexpress S-ATA

RP-X

Fig. 4.22 Block diagram of RP-X

Internal Bus

Sequence Manager (SEQM)

LS
Cells

Local
Memories

Array Control Bus

ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

MLT ALU

ALU
ALU
ALU
ALU
ALU
ALU
ALU

ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

LS CRAM

MLT
MLT
MLT
MLT
MLT
MLT
MLT

LS
LS
LS
LS
LS
LS
LS
LS
LS

CRAM
CRAM
CRAM
CRAM
CRAM
CRAM
CRAM
CRAM
CRAM

Arithmetic Cell Array

Crossbar Network (XB)

Configuration Manager (CFGM)

Fig. 4.23 Structure of dynamic recon fi gurable processor FE-GA

4.4.2 Dynamically Recon fi gurable Processor FE-GA

Figure 4.23 illustrates the structure of the FE-GA. It is a dynamic reconfigurable
processor consisting of an arithmetic cell array of 24 16-bit ALUs and eight 16-bit
multipliers, ten pairs of a load/store (LS) cell, and a local memory (CRAM). The
cell array and LS cells are connected by crossbar network (XB). The array is
con fi gured by a con fi guration manager (CFGM) and controlled by a sequence man-
ager (SEQM) via an array control bus. The SEQM outputs interrupts and DMA