Chip Implementations - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 143

Table 4.6 RP-X speci fi cations
Process technology 45-nm, 8-layer Cu, triple-Vth, CMOS

Chip size 153.76 mm 2 (12.4 mm × 12.4 mm)

Supply voltage 1.0-1.2 V (internal), 1.2/1.5/1.8/2.5/3.3 V (I/O)

Clock frequency 648 MHz (SH-X4), 324 MHz (FE-GA, MX-2)

Total power consumption 3.07 W (648 MHz, 1.15 V)

Processor cores
and
performances

8× SH-X4 CPU 13.7 GIPS (Dhrystone 2.1, 8-core total)

FPU 36.3 GFLOPS (8-core total)

4× FE-GA 41.5 GOPS (4-core total)

2× MX-2 36.9 GOPS (2-core total)

Programmable
Special-purpose cores

VPU5 (video processing unit) for MPEG2, H.264, VC-1
SPU (sound processing unit) for AAC, MP3

Total performances and power 114.7 GOPS, 3.07 W, 37.3 GOPS/W (648 MHz, 1.15 V)

External interfaces 2x DDR3-SDRAM (32-bit, 800 MHz), SRAM

PCI-Express (rev 2.0, 2.5 GHz, 4 lanes), Serial ATA

The eight SH-X4 cores achieved 13.7 GIPS at 648 MHz measured using the
Dhrystone 2.1 benchmark. Four FE-GAs, dynamically reconfigurable processors,
were integrated and attained a total performance of 41.5GOPS and a power con-
sumption of 0.76 W. Two 1,024-way MX-2s were integrated and attained a total
performance of 36.9GOPS and a power consumption of 1.10 W. Overall, the
efficiency of the RP-X was 37.3 GOPS/W at 1.15 V excluding special-purpose
cores of a VPU5 and an SPU. This was the highest among comparable processors.
The operation granularity of the SH-X4, FE-GA, and MX-2 processors are 32 bits,
16 bits, and 4 bits, respectively, and thus, we can assign the appropriate processor
cores for each task in an effective manner.
Figure 4.22 illustrates the structure of the RP-X. The processor cores of the
SH-X4, FE-GA, and MX-2; the programmable special-purpose cores of the
VPU5 and SPU; and the various modules are connected by three SuperHyway
buses to handle high-volume and high-speed data transfers. SuperHyway-0 con-
nects the modules for an OS, general tasks, and video processing, SuperHyway-1
connects the modules for media acceleration, and SuperHyway-2 connects media
IPs except for the VPU5. Some peripheral buses and modules are not shown in
the fi gure.
A data transfer unit (DTU) was implemented in each SH-X4 core to transfer data
to and from the special-purpose cores or various memories without using CPU
instructions. In this kind of system, multiple OSes are used to control various func-
tions, and thus, high-volume and high-speed memories are required.