Chip Implementations - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 135

Table 4.3 RP-2 speci fi cations
Process technology 90-nm, 8-layer Cu, triple-Vth, CMOS

Chip size 104.8 mm 2 (10.61 mm × 9.88 mm)

Supply voltage 1.0 V (internal), 1.8/3.3 V (I/O)

Clock frequency 600 MHz

SH-X3 core Size 6.6 mm 2 (3.36 mm × 1.96 mm)

I/D-cache 16-KB 4-way set-associative (each)

ILRAM/OLRAM 8 KB/32 KB

URAM 64 KB

Centralized shared memory (CSM) 128 KB

External interface s DDR2-SDRAM, SRAM

Performance CPU 8,640 MIPS (Dhrystone 2.1, 8-core total)

FPU 33.6 GFLOPS (peak, 8-core total)

Chip power 2.8 W (600 MHz, 1.0 V, room temperature, Dhrystone 2.1)

normal mode, respectively, although these modes took some time to stop and start
the CPU core and to save and return the cache. The execution time increased by
79.5% at 300 MHz, but the power consumption decreased, and the required energy
decreased by 5.2%.

4.3 RP-2 Prototype Chip

The RP-2 is a prototype multicore chip with eight SH-X3 CPU cores (see Sect.
3.1.7 ) [ 15- 17 ]. It was fabricated in a 90-nm CMOS process that was the same pro-
cess used for the RP-1. The RP-2 achieved a total of 8,640 MIPS at 600 MHz by the
eight SH-X3 cores measured with the Dhrystone 2.1 benchmark. Because it is
difficult to lay out the eight cores close to each other, we did not select a tightly
coupled cluster of eight cores. Instead, the RP-2 consists of two clusters of four
cores, and the cache coherency is maintained in each cluster. Therefore, the inter-
cluster cache coherency must be maintained by software if necessary.

4.3.1 RP-2 Speci fi cations

Table 4.3 summarizes the RP-2 specifications. The RP-2 integrates eight SH-X3
cores as two clusters of four cores, DDR2-SDRAM and SRAM memory interfaces,
DMA controllers, and some peripheral modules. Figure 4.13 illustrates a block dia-
gram of the RP-2. The arrows to/from the SuperHyway indicate connections from/
to initiator/target ports, respectively.