Hardware Reference
In-Depth Information
Fig. 4.9
Chip micrograph
of RP-1
1.00
0.75
1 Thread
2 Threads
4 Threads
Barrier
0.50
0.25
0
FFT
LU
Radix
Water
Fig. 4.10
Execution time of SPLASH-2 suite
timing closure of the core, and (2) the whole chip was laid out with instancing the
core four times.
4.2.7
Performance Evaluations
We evaluated the processing performance and power reduction in parallel process-
ing on the RP-1. Figure 4.10 plots the time required to execute the SPLASH-2 suite
[ 14 ] depending on the number of threads on an SMP Linux system. The RP-1
reduced the processing time to 50.5-52.6% and 27.1-36.9% with two and four
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