Chip Implementations - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 130

3. Snoop Acknowledge and Invalidate Request
4. Data Cache Update
5. Invalidate Acknowledge

The “Snoop Acknowledge” is moved from the sixth to the third step by eliminat-
ing the wait of the “Invalidate Acknowledge,” and the late response of the slow core
does not affect the operation of the fast core. In the optimized sequence, the SNC is
busy for some cycles after the “Snoop Acknowledge,” and the next “Core Snoop
Request” must wait if the SNC is still busy. However, this is rare for ordinary
programs.
The sequence of another case, a “read miss and hit to another core's modified
line,” which is the last case in the table, is as follows:

1 . Core Snoop Request : A data read of core #0 misses its cache and sends a “Core
Snoop Request” of the access address to the SNC.
2 . DAA Update : The SNC searches the DAA of all the cores and changes the states
of the hit lines from “Modified” to “Shared.”
3 . Data Transfer Request : The SNC sends a “Data Transfer Request” to the core of
the hit line for the cache fill data of core #0.
4 . Data Cache Update : The requested core reads the requested data and changes
the states of the corresponding line of the DAA to “Shared.” The processing time
depends on each core's ICLK.
5 . Data Transfer Response and Write Back Request : The requested core returns the
requested data and requests a write back to the SNC.
6 . Snoop Acknowledge and Write Back Request : The SNC returns “Snoop
Acknowledge” to core #0 with the fill data and requests a write back of the
returned data to the main memory.
7 . Data Cache Update 2 : Core #0 completes the “Read” operation by replacing a
cache line with the fi ll data.

In this case, core #0 must wait for the fill data, and the early “Snoop Acknowledge”
is impossible.

4.2.5 SuperHyway Bus

It would require too much time and money to design an SoC consisting of a lot of
originally designed modules. Therefore, we make a module that is reusable and
refer to it as a HW-IP. A standard and highly efficient method is needed to connect
the HW-IPs. An on-chip system bus called SuperHyway is a packet-based split
transaction bus used to connect the HW-IPs, and transactions may contain up to 32
bytes of data. The bus is compatible with Virtual Socket Interface (VSI) protocols.
It seamlessly connects to VSI virtual-component libraries.
Effective support of high-speed, multi-initiator, multi-target data transfer is
important for cost-effective SoC implementations. Such data transfer mechanisms