Chip Implementations - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 126

Table 4.1 RP-1 speci fi cations
Process technology 90-nm, 8-layer Cu, triple-Vth, CMOS

Chip size 97.6 mm 2 (9.88 mm × 9.88 mm)

Supply voltage 1.0 V(internal), 1.8/3.3 V(I/O)

Clock frequency 600 MHz

SH-X3 core Size 2.60 mm × 2.80 mm

I/D-cache 32-KB 4-way set-associative (each)

ILRAM/OLRAM 8 KB/16 KB

URAM 128 KB (uni fi ed)

Snoop controller (SNC) Duplicated address array (DAA) of four D-caches

Centralized shared memory (CSM) 128 KB

External interfaces DDR2-SDRAM, SRAM, PCI-Express

Performance CPU 4,320 MIPS (Dhrystone 2.1, 4-core total)

FPU 16.8 GFLOPS (peak, 4-core total)

Package 554-pin FCBGA, 29 mm × 29 mm

Chip power 3 W (typical, 1.0 V)

using the Dhrystone 2.1 benchmark. It supports both symmetric and asymmetric
multiprocessor (SMP and AMP) features for embedded applications. The SMP and
AMP modes can be mixed to construct a hybrid system of the SMP and AMP. Each
core can operate at different frequencies and can stop individually with maintaining
its data cache coherency, while the other processors are running in order to achieve
both the maximum processing performance and the minimum operating power for
various applications.

4.2.1 RP-1 Speci fi cations

Table 4.1 summarizes the RP-1 specifications. The RP-1 integrates four SH-X3
cores with a snoop controller (SNC) to maintain the data cache coherency among
the cores, DDR2-SDRAM and SRAM memory interfaces, a PCI-Express interface,
some HW-IPs for various types of processing, and some peripheral modules. The
HW-IPs include a DMA controller, a display unit, and accelerators. Each SH-X3
core includes a CPU, an FPU, 32-KB 4-way set-associative instruction and data
caches, a 4-entry instruction TLB, a 64-entry unified TLB, an 8-KB instruction
local RAM (ILRAM), a 16-KB operand local RAM (OLRAM), and a 128-KB user
RAM (URAM).
Figure 4.4 illustrates a block diagram of the RP-1. The four SH-X3 cores, a snoop
controller (SNC), and a debug module (DBG) constitute a cluster. The HW-IPs are
connected to an on-chip system bus (SuperHyway). The arrows to/from the SuperHyway
indicate connections from/to initiator/target ports, respectively. The details of the
SH-X3 cluster and SuperHyway are described in the following sections.