Hardware Reference
In-Depth Information
and an SH2A-DUAL [ 7 ] and an SH-Navi3 [ 8 ] are the multicore SoC products of
this enhancement type. The transition from single core chips to multicore ones
seems to have been successful on the hardware side, and various multicore products
are already on the market. However, various issues still need to be addressed for
future multicore systems.
The first issue concerns memories and interconnects. Flat memory and intercon-
nect structures are the best for software, but hardly possible in terms of hardware.
Therefore, some hierarchical structures are necessary. The power of on-chip inter-
connects for communications and data transfers degrade power efficiency, and a
more effective process must be established. Maintaining the external I/O perfor-
mance per core is more difficult than increasing the number of cores, because the
number of pins per transistors decreases for finer processes. Therefore, a break-
through is needed in order to maintain the I/O performance.
The second issue concerns runtime environments. The performance scalability
was supported by the operating frequency in single core systems, but it should be
supported by the number of cores in multicore systems. Therefore, the number of
cores must be invisible or virtualized with small overhead when using a runtime
environment. A multicore system will integrate different subsystems called domains.
The domain separation improves system reliability by preventing interference
between domains. On the other hand, the well-controlled domain interoperation
results in an efficient integrated system.
The third issue relates to the software development environments. Multicore sys-
tems will not be efficient unless the software can extract application parallelism and
utilize parallel hardware resources. We have already accumulated a huge amount of
legacy software for single cores. Some legacy software can successfully be ported,
especially for the integration type of multicore SoCs like the SH-Mobile G series.
However, it is more difficult with the enhancement type. We must make a single
program that runs on multicore or distribute functions now running on a single core
to multicore. Therefore, we must improve the portability of legacy software to the
multicore systems. Developing new highly parallel software is another issue. An
application or parallelization specialist could do this, although it might be necessary
to have specialists in both areas. Some excellent research has been done on auto-
matic parallelization compilers, and the products of such compilers are expected to
be released in the future. Further, we need a paradigm shift in the development, for
example, a higher level of abstraction, new parallel languages, and assistant tools
for effective parallelization.
4.2
RP-1 Prototype Chip
The RP-1 is the first multicore chip with four SH-X3 CPU cores (see Sect. 3.1.7)
[ 9- 13 ]. It was fabricated as a prototype chip using a 90-nm CMOS process to accel-
erate the research and development of various embedded multicore systems. The
RP-1 achieved a total of 4,320 MIPS at 600 MHz by the four SH-X3 cores measured
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