Hardware Reference
In-Depth Information
With two-domain (stream-rate and pixel-rate) processing, two parallel pipelines
for macroblock processing, and tile-based address translation circuits, the video
processing unit consumed 95 mW of power in real-time decoding of a full HD
H.264 stream at an operating frequency of 162 MHz at 1.1 V.
The video processing unit in the test chip supports four video coding standards:
H.264, MPEG-2, MPEG-4, and VC-1. Moreover, by changing the firmware and
system software, this unit can support other coding standards such as AVS or H.263
or some proprietary video coding technologies based on a supported video coding
standard as noted above.
A successor to the H.264 standard is currently being developed by the Joint
Collaborative Team on Video Coding (JCT-VC) and will be called the High
Efficiency Video Coding (HEVC) standard [78???]. HEVC aims to substantially
improve coding efficiency compared to the H.264 High Profile, that is, reduce bit-rate
requirements by half with comparable visual quality at the expense of increased
computational complexity. Thus, efficient parallel operation is strongly desired in
order to satisfy both high performance and low-power consumption for video codec
design at the architecture level.
References
1. Daniels RG (1996) A participant's perspective. IEEE Micro 16(2):8-15
2. Gwennap L (1996) CPU technology has deep roots. Microprocessor Report 10(10):9-13
3. Nakamura H et al (1983) A Circuit Methodology for CMOS Microcomputer LSIs. ISSCC Dig
Tech Papers:134-135
4. Patrick P. Gelsinger (2001) Microprocessors for the New Millennium Challenges, Opportunities,
and New Frontiers. ISSCC Dig Tech Papers, Session 1.3
5. Weicker RP (1984) Dhrystone: a synthetic programming benchmark. Commun ACM 27(10):
1013-1030
6. Kawasaki S (1994) SH-II a low power RISC microprocessor for consumer applications. HOT
Chips VI:79-103
7. Hasegawa A et al (1995) SH-3: high code density, low power. IEEE Micro 15(6):11-19
8. Arakawa F, et al (1997) SH4 RISC Multimedia Microprocessor. HOT Chips IX Symposium
Record:165-176
9. Nishii O, et al (1998) A 200 MHz 1.2 W 1.4GFLOPS microprocessor with graphic operation
unit. ISSCC Dig Tech Papers:288-289, 447
10. Arakawa F et al (1998) SH4 RISC multimedia microprocessor. IEEE Micro 18(2):26-34
11. Biswas P et al (2000) SH-5: the 64 bit SuperH architecture. IEEE Micro 20(4):28-39
12. Uchiyama K et al (2001) Embedded processor core with 64-bit architecture and its system-
on-chip integration for digital consumer products. IEICE Trans Electron E84-C(2):139-149
13. Arakawa F (2001) SH-5: A First 64-bit SuperH Core with Multimedia Extension. HOT Chips
13 Conference Record
14. Arakawa F et al (2004) An embedded processor core for consumer appliances with 2.8GFLOPS
and 36 M Polygons/s FPU. ISSCC Dig Tech Papers 1:334-335, 531
15. Ozawa M, et al (2004) Pipeline Structure of SH-X Core for Achieving High Performance and
Low Power, COOL Chips VII Proceedings, vol. I:239-254
16. Arakawa F et al (2004) An embedded processor core for consumer appliances with 2.8GFLOPS
and 36 M polygons/s FPU. IEICE Trans Fundamentals E87-A(12):3068-3074
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