Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 117

Table 3.20 Specifications of VPU and measured power consumption
Technology 45-nm, 8-layer, triple-Vth, CMOS

Circuit size 4.0 MGate logic and 300 kB SRAM

Supply voltage 1.1 V (1.0-1.2 V)

Clock frequency 162 MHz

Performance 1,920 × 1,080 × 30 fpts, 40 Mbps

Supported video coding
standard and measured power
consumption

Standard Pro fi le Level Decoding Encoding

H.264 High 4.1 95 mW 162 mW

MPEG-2 Main High 70 mW 130 mW

MPEG-4 Advanced simple 5 77 mW 134 mW

VC-1 Simple Medium

Main High 107 mW n/a

Advanced 3

Fig. 3.91 Micrograph of test chip in 45-nm CMOS

less than 1,200 in H.264 encoding and less than 1,000 in H.264 decoding. In addi-
tion to the H.264 processing, the average macroblock-processing cycle for MPEG-2,
MPEG-4, and VC-1 is less than 1,200, which means the video codec is capable of
full HD real-time processing at an operating frequency of 162 MHz.
Table 3.20 lists specifications of the video codec and the measured results for
power consumption in the processing of full HD video at 30 fps. With 45-nm CMOS
technology, the codec consumed 162 mW in encoding and 95 mW in decoding of
H.264 High Profile at 1.10 V at room temperature. Figure 3.91 is a micrograph
of the test chip, which is overlaid with the layout of the video processing unit.

3.4.5 Conclusion

A multistandard, size-scalable, low-power video codec including one stream pro-
cessor and six image-processing processors has been integrated in 45-nm CMOS.