Hardware Reference
In-Depth Information
a
64bit
64bit
64bit
Sync
Sync
Sync
Source1/2
Source1/2
Source1/2
Opecode
Opecode
Opecode
Destination
Destination
Destination
Count
Count
Count
Width
Width
Width
Pitch
Pitch
Pitch
Synchronization
between PUs
Load/store
instruction
Source
Destination
Pitch
Loading
PU
Reg0
Reg1
Reg2
Reg3
Reg4
Reg5
Reg6
Reg7
Width
ALU
Data
Media
PU
-
Width
Width
Example of SIAD instruction format
b
Register File
Src1
Src2
Shifter / extender
X
X
X
X
X
X
add
add
Barrel
shifter
Barrel
shifter
shifter
SIAD ALU structure
Fig. 3.89
SIAD processor architecture and instruction format
data, performing image processing, and storing data. Arrays of data are specifiable
as the operands for several single instructions of the PUs, so they are capable of
handling multiple horizontal data as vectors. This aspect of the PIPE can reduce the
number of cycles required for operations such as pre-/post-transposition processing,
as well as the code size and instruction fetches. Reducing instruction fetches from
the shared instruction memory reduces power consumption. Overall, the PIPE
improves the efficiency with which 2D data and instructions are supplied.
A single instruction multiple data (SIMD) architecture performs the same opera-
tion on multiple data simultaneously using multiple processing elements. In gen-
eral, the SIMD can only handle a pair of source data, which is in the horizontal
pixels of images. A major cause of performance degradation in 2D image process-
ing is that one instruction can handle only single source data. To solve this issue, 2D
vector data in a single instruction are taken into account.
Figure 3.89a shows a single instruction with arrayed data (SIAD) instruction
format. The width and count fields specify multiple source data as multiple vector data.
Search WWH ::




Custom Search