Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 109

PLL PLL

Static
module
stop
registers

Static
module
stop
registers

Macroblock-level
signal processing

Macroblock-level
signal processing

Clock driver
for module

Clock driver
at sub-module

Clock driver
at sub-module

Clock start/stop requests

Clock start/stop requests

Dynamic clock control at sub-module level Dynamic clock control at sub-module level

Controlled by software

Fig. 3.83 Hierarchical clock control for full HD video processing

Time slot Macroblock-processing

Time

Encoding process

n n Stage0 DMA read

Stage1 Coarse ME
Stage2 Fine ME

n n

n n

Stage3 Transform

n n

Stage4 Symbol coding n n

n n

Stage4 De-blocking

n n Stage5 DMA write

Data flow

Clock supply is stopped

Fig. 3.84 Dynamic power control in macroblock-level pipeline processing

3.4.2.4 Hierarchical Power Management

Figure 3.83 shows how the clock domains are divided at the submodule level. The
power management architecture consists of multiple domains, which are controlled
independently using video codec processing characteristics. A new layer of control
is set up between the static module stop controlled by software and the bit-grained
clock gating. We defined clock domains for each submodule of the video codec.
Each clock domain corresponds to a macroblock processing pipeline stage and is
also a unit of hierarchical synthesis and layout. The clock signals in the respective
domains are switched in accordance with the time reference defined by the macro-
block processing.
Figure 3.84 illustrates the dynamic power management in the pipeline for
macroblock processing. Data are processed in a macroblock-based pipeline manner.
The time reference defined 1,200 clock cycles at 162 MHz. Variable-length coding
inherently lacks a fixed processing time. The clock supply for each block is inde-
pendently cut off as soon as it finishes its required processing. This scheme reduces
the amount of power consumed by the clock drivers. Dynamic power consumption
is reduced by 27% by using this technique [ 76 ] .