Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 108

Fig. 3.81 Dual macroblock-
level pipeline processing

A B C

D X

IPU
#1

IPU
#0

Macroblock

Data flow

a b c

IPU #n

Data flow

IPU #1

SPPa #0 SPPb #0 HWC #0 #m #n

IPU #1

Data flow

SRS SRS SRS SRS SRS

SPPa #0 SPPb #0 HWC #0 #m #n

IPU #0

IPU #0

IPU #0

SRS SRS SRS SRS SRS

L-MEM

L-MEM

L-MEM

SRS

SRS SRS SBUS

1 IPU 2 IPUs n IPUs

Fig. 3.82 Con fi guration of image processing unit and data fl ows

To ensure real-time processing, we specified 1,200 as the upper bound on the
number of clock cycles for processing each macroblock. The value 1,200 ensures
that the overall image processing unit is capable of handling full HD operations at
less than 162 MHz. By varying the combinations of clock frequency and the number
of image processing units, our approach provides reasonable scalability across the
range from SD to full HD and even larger screen sizes while still only requiring
the single shared-line memory. Figure 3.82 depicts examples of IPU configurations
and data flows between the IPUs and L-MEM along with the SBUS. For example,
an LSI with a single IPU is a good option for applications that require the handling
of SD video and is capable of doing so at an operating frequency of 54 MHz.