Hardware Reference
In-Depth Information
3.4
Video Processing Unit
This section introduces the architecture and circuit techniques for video encoding/
decoding processors. This video codec processor is embedded in the heterogeneous
multicore chip as a special-purpose processor (SPP), which is described in Chap. 2.
3.4.1
Introduction
Consumer audiovisual devices such as digital video cameras, mobile handsets, and
home entertainment equipment have become major drivers for raising the perfor-
mance and lowering the power consumption of signal processing circuits. Market
trends in the field of consumer video demand larger picture sizes, higher bit rates,
and more complex video processing. In video coding, the wide range of consumer
applications requires the ability to handle video resolutions across the range from
standard definition (SD, i.e., 720 pixels by 480 lines) to full high definition (full HD,
i.e., 1,920 pixels by 1,080 lines) encoded in multiple video coding standards such as
H.264, MPEG-2, MPEG-4, and VC-1. H.264 [
64
] is one of the latest standards for
motion-estimation-based codecs. It contains a number of new features [
65,
66
] that
allow it to compress video much more effectively than older standards, but it requires
more processing power. The availability of context-adaptive binary arithmetic coding
(CABAC) is considered one of the primary advantages of the H.264 encoding
scheme, since it provides more efficient data compression than other entropy encoding
schemes, including context-adaptive variable-length coding (CAVLC). However, it
also requires considerably more processing. The trade-off between high performance
and low-power consumption is a key focus of video codec design for advanced
embedded systems, especially for mobile application processors [
28,
67-
69
] .
Many video coding processors have been proposed. Generally, these codecs use
one of two approaches. The first approach constructs video encoding and decoding
software on homogenous high-performance processor cores [
67,
68
] . This approach,
which handles multiple video coding standards by changing the software or
firmware, suffers from large power consumption and lack of performance. A dual-
core DSP operating at 216 MHz [
67
] offers up to SD video, and an eight-core media
processor operating at 324 MHz [
68
] supports high definition (HD, i.e., 1,280 pixels
by 720 lines) at most. The second approach aims to develop dedicated video coding
hardware. While dedicated circuits can minimize power consumption, the dedicated
encoders and decoders described in previous reports [
70-
73
] have dif fi culty in per-
forming all of the media processing that is indispensable for an embedded device
such as a modern smart phone [
28,
67-
69
]. In addition, few of these video codecs
can handle video streams at more than 20 megabits per second (Mbps), so they have
difficulty in supporting full HD high-quality video.
In response to these issues, a video processing unit (VPU) has been designed based
on a heterogeneous multicore processor in order to achieve both high performance
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