Hardware Reference
In-Depth Information
Table 3.16
Booth encoding table
B[
i
+ 1] (XH) B[
i
] (X) B[
i
−1] (F
−1
) Operation
Shift (
D
) Complement (
F
) Nop (
N
)
0
0
0
0(NOP)
0
0
0
0
0
1
+A(ADD)
0
0
1
0
1
0
+A(ADD)
0
0
1
0
1
1
+2A(SHIFT & ADD)
1
0
1
1
0
0
−2A(SHIFT & SUB)
1
1
1
1
0
1
−A(SUB)
0
1
1
1
1
0
−A(SUB)
0
1
1
1
1
1
0(NOP)
0
1
0
V
alid Reg.
V
O
<2>
I<2>
I<1>
I<0>
O<1>
O
<0>
Booth-
Encoder
N
F
Temp. Reg.
D
Carry Reg.
0
XH
I2
C
out
C
I1
FA
1
Cin
Sum
Temp. Reg.
<0>
0
X
I2
Cout
<0>
I1
FA
1
Sum
<0>
S
Cin
Shift-Compensate Reg.
MUX
MUX
Left/Right
Left/Right
IN_L<1:0>
IN_R<1:0>
OUT<1:0>
Output_Enable
Fig. 3.67
Circuit diagram of processing element
which operates according to Table
3.16
. D/F/N registers, which store the encoded
results of the Booth's encoder, are implemented to control the way of generating
partial products. That is, D switches the multiplicand shifts (1 bit shift) or not, F
switches the multiplicand inverts for complementing or not, and N switches whether
the partial product is valid or not. In addition, S is the register for shift compensation
which functions when D register is set to 1, and V register is implemented for vali-
dating the function of each PE. Figure
3.68
shows the proposed operation flow of a
MAC operation. At first, 2 bits of the multiplier are loaded to the temporary register
of PE, XH, and X, and the values of F/D/N registers are fixed with Booth's encod-
ing. Next, 2 bits of the multiplicand are loaded to XH and X registers, and also 2 bits
of the accumulator region are added with the data in XH, X, and S registers at the
conditions of D/F/N registers. These sequences are realized by programming the
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