Hardware Reference
In-Depth Information
a
b
i
i
1
2
1
2
o
1
o
1
o
2
i, o
2
o
1
,o
2
o
1
,o
2
F
F
4
i
c
o
1
,o
2
i
o
2
1
2
F
4
o
1
i
u
1
,u
2
,v
1
,v
2
u
1
,u
2
,v
1
,v
2
u
1
,u
2
,v
1
,v
2
u
1
,u
2
,v
1
,v
2
d
v
1
e
1
v
1
,v
2
u
1
a
1
c
1
b
1
u
2
u
2
o
1
d
1
i
c
2
u
2
e
4
u
1
u
1
o
1
c
4
b
4
v
1
v
2
o
2
b
2
d
2
v
2
d
4
aF
i
o
2
u
2
v
1
,v
2
v
1
v
2
u
1
eF
cF
bF
v
1
e
2
v
2
dF
\
.IO/
?
;(
c
)FAof.C
Fig. 3.11
Illustration of Exam
pl
e
3.29
.(
a
)FAofC ;(
b
)FAofC
\
.IO/
?
/
*
U
[
V
;(
d
)FAofA
\
.C
\
.IO/
?
/
*
U
[
V
the automaton of .U V /
?
in Fig.
3.10
b
0
.The
dc
state of the former automaton is
split into states
dc1
and
dc2
because .
UV
/
?
restricts the acceptance to words that
terminate by a symbol in V ; therefore the original
dc
state that can accept any word
in .U
[
V/
?
is replaced by two states to accept only the words in .U V /
?
.U
[
V/
?
.
For logic synthesis applications, we assume that M
A
and M
C
are complete FSMs
and we require that the solution is a complete FSM too. This is obtained by applying
Procedure
3.1.4
to S
FSM
, yielding Prog.S
FSM
/,thelargest.I
2
[
U /.V
[
O
2
/-
[
O
2
//
?
.
progressive FSM language
..I
2
[
U /.V
Search WWH ::
Custom Search