Hardware Reference
In-Depth Information
a
i
1
v
1
/u
2
o
1
b
i
1
v
1
/u
1
o
1
i
2
v
1
/u
1
o
1
a
b
i
2
/o
2
1
i
1
/o
1
i
1
v
2
/−−
i
1
v
2
/−−
i
2
v
1
/−−
i
2
v
2
/−−
i
2
v
2
/−−
c
u
2
/v
1
a
1
dc
c
−−/−−
−/−
d
e
i
1
v
1
/u
2
o
1
u
2
/v
1
i
1
v
1
/u
1
o
1
u
1
/v
1
i
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v
2
/u
1
o
1
a
b
a
1
b
1
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/v
2
u
1
/v
2
i
1
v
2
/u
1
o
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/u
2
o
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1
/u
1
o
1
i
2
v
2
/u
2
o
1
i
2
v
1
/u
2
o
1
c
dc
−−/−−
−−/−−
e
g
u
2
/v
1
i
1
v
1
/u
2
o
1
i
1
v
1
/u
1
o
1
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1
/v
1
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1
/u
2
o
1
a
b
a
1
b
1
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/u
1
o
2
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v
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/u
1
o
2
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v
1
/u
1
o
1
i
1
v
2
/u
2
o
2
u
2
/v
2
u
1
/v
2
i
2
v
2
/u
2
o
2
i
1
v
1
/u
1
o
2
i
1
v
2
/u
2
o
1
i
2
v
1
/u
2
o
1
i
2
v
2
/u
1
o
2
c
c
1
u
1
/v
2
u
2
/v
2
Fig. 3.5
Illustration of Example
3.19
.(
a
) FSM M
A
;(
b
) FSM M
C
;(
c
)FSMM
X
;(
d
)FSMM
A
;
(
e
) FSM M
X
;(
f
) FSM M
A
;(
g
) FSM M
X
For logic synthesis applications, we assume that M
A
and M
C
are complete FSMs
and we require that the solution is a complete FSM too. This is obtained by applying
Procedure
3.1.2
to S
FSM
, yielding Prog.S
FSM
/,thelargest.I
2
U/-progressive
FSM language
.I
2
U
V
O/
?
. Notice that an .I
2
U/-progressive solution
might not exist, and in that case Procedure
3.1.2
returns an empty language.
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