Hardware Reference
In-Depth Information
107. A. Petrenko, N. Yevtushenko, Solving asynchronous equations. in
Formal Description
Techniques and Protocol Specification, Testing and Verification - FORTE XI/PSTV XVIII '98
,
eds. by S. Budkowski, A. Cavalli, E. Najm. (Kluwer, Dordrecht, 1998), pp. 231-247
108. A. Petrenko, N. Yevtushenko, Conformance tests as checking experiments for partial nonde-
terministic FSM. in
FATES 2005
, eds. by W. Grieskamp, C. Weise. volume 3997 of
Lecture
Notes in Computer Science
. (Springer, Berlin, 2005), pp. 118-133
109. A. Petrenko, N. Yevtushenko, G.V. Bochmann, Fault models for testing in context. in
IFIP
TC6/ 6.1 international conference on formal description techniques IX/protocol specification,
testing and verification XVI on Formal description techniques IX : theory, application and
tools
, pp. 163-178, London, UK, 1996. Chapman & Hall, Ltd.
110. A. Petrenko, N. Yevtushenko, G.V. Bochmann, Testing faults in embedded components. in
Proceedings of the 10th International Workshop on Testing of Communicating Systems - IFIP
IWTCS97
, pp. 272-287, Sept 8-10, 1997
111. A. Petrenko, N. Yevtushenko, R. Dssouli, Testing strategies for communicating finite state
machines. in
IFIP WG 6.1 International Workshop on Protocol Test Systems (7th : 1994 :
Tokyo, Japan)
, eds. by T. Mizuno, T. Higashino, N. Shiratori. (Chapman & Hall, London,
1995), pp. 193-208
112. A. Petrenko, N. Yevtushenko, A. Lebedev, A. Das, Non-deterministic state machines in
protocol conformance testing. in
IFIP TC6/WG6.1 International Workshop on Protocol Test
Systems (6th : 1993 : Pau, France)
, ed. by O. Rafiq. (North-Holland, Amsterdam, 1994),
pp. 363-378
113. A. Petrenko, N. Yevtushenko, G.V. Bochmann, Testing deterministic implementations from
nondeterministic FSM specifications. in
Testing of Communicating Systems, Selected pro-
ceedings of the IFIP TC6 9th international workshop on Testing of communicating systems
.
(Chapman & Hall, Ltd., London, UK, 1996), pp. 125-140
114. A. Petrenko, N. Yevtushenko, G.V. Bochmann, R. Dssouli, Testing in context: framework and
test derivation. Comput. Commun.
19
(14), 1236-1249 (1996)
115. C.P. Pfleeger, State reduction in incompletely specified finite state machines. IEEE Trans.
Comput. 1099-1102 (1973)
116. C. Pixley, A computational theory and implementation of sequential hardware equivalence. in
DIMACS Technical Report 90-31, volume 2, Workshop on Computer-Aided Verification
,eds.
by R. Kurshan, E.M. Clark (1990)
117. The Grail+ Project, A Symbolic Computation Environment for Finite-State Machines,
Regular Expressions, and Finite Languages. Software package, available at
http://www.csd.
118. H. Qin, P. Lewis, Factorisation of finite state machines under strong and observational
equivalences. Formal Aspect. Comput.
3
, 284-307 (1991)
119. P. Ramadge, W. Wonham, The control of discrete event systems. Proc. IEEE
77
(1), 81-98
(1989)
120. R. Ranjan, A. Aziz, R. Brayton, B. Plessier, C. Pixley, Efficient BDD algorithms for FSM
synthesis and verification. International Workshop on Logic Synthesis, 1995
121. J.-K. Rho, F. Somenzi, Don't care sequences and the optimization of interacting finite state
machines. IEEE Trans. Comp. Aided Des.
13
(7), 865-874 (1994)
122. M. Roggenbach, Determinization of B uchi-automata. In
Automata logics, and infinite games:
a guide to current research
, (Springer, New York, 2002), pp. 43-60
123. K. Rohloff, S. Lafortune, PSPACE-completeness of modular supervisory control problems.
Discrete Event Dyn. Syst. Theo. Appl.
15
(2), 145-167 (2005)
124. K.R. Rohloff,
Computations on Distributed Discrete-Event Systems
. PhD thesis, University
of Michigan, May 2004
125. E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan,
R. Brayton, A. Sangiovanni-Vincentelli, SIS: A system for sequential circuit synthesis.
Technical report, Tech. Rep. No. UCB/ERL M92/41, Berkeley, CA, May 1992.
126. J. Shallit,
A Second Course in Formal Languages and Automata Theory
. (Cambridge U.P.,
2009)
Search WWH ::
Custom Search