Hardware Reference
In-Depth Information
conditions when the output of the node does not influence the values produced by the
primary outputs (after any number of iterations, given the same input sequence and
initial latch states). However the latch outputs may change, as long as the primary
outputs are unaffected over all iterations.
The maximum sequential flexibility (MSF) is a superset of the combinational
flexibility (CF) at a node, since the latter constrains all outputs to be the same, while
the former allows latch outputs to be different. For instance, MSF may be a superset
of CF due to presence of unreachable latch outputs (states), so that some primary
input combinations can never occur and therefore we can set them to assume any
value (see the command extract seq dc in SIS).
An additional source of flexibility are equivalent states, so that for certain input
combinations more than one latch value is acceptable. For instance, in the following
FSM specified in kiss format, states st1 and st2 are equivalent.
.i 1
.o 1
.s 2
.p 4
0 st1 st1 1
1 st1 st2 0
0 st2 st2 1
1 st2 st1 0
.end
With the encoding st1 D 0 and st2 D 1, we obtain the logic eq ua tions (X input,
Z output, cs and ns present and next state) ns D X ˚ cs, Z D X. The output of
the XOR gate has no combinational flexibility or due to unreachable states, however
it does not affect the primary output Z, thus all four minterms of ns are don't care
minterms due to equivalent states.
Latch encoding has an important effect on introducing minterm don't cares.
Consider the following FSM specified in kiss format:
.i 1
.o 1
.s 4
.p 8
0 st1 st2 1
1 st1 st3 0
0 st2 st1 1
1 st2 st4 0
1 st3 st1 1
0 st3 st4 0
1 st4 st2 1
0 st4 st3 0
.end
Are there equivalent states ?
With the encoding st1 D 00, st2 D 01, st3 D 10, st4 D 11. obtain the logic
equations for ns1.X; cs0; cs1/, ns0.X; cs0; cs1/ and Z.X; cs0; cs1/ (X input, Z
output, cs0; cs1 and ns0; ns1 present and next states).
Are there don't care minterms due to equivalent states ?
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