Hardware Reference
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.table Acc #all states are accepting
1
.table i o CS ->NS
0 0 st0 st0
1 1 st0 st1
0 0 st1 st1
1 1 st1 st2
...
0 0 st31 st31
1 1 st31 st0
.end
The latter format would apply also if the counter FSM would have say 33 states,
whereas the former format would not. Consider the following counter with 33 states:
.i 1
.o 1
.s 33
.p 66
0 st0 st0 0
1 st0 st1 1
0 st1 st1 0
1 st1 st2 1
...
0 st31 st31 0
1 st31 st32 1
0 st32 st32 0
1 st32 st0 1
.end
The previous AUT description would be extended easily as follows (say in
the file counter33.aut ):
.model counter33.aut
.inputs i o
.outputs Acc
.mv CS, NS 33 st0 st1 ... st31 st32
.latch NS CS
.reset CS
0
.table Acc #all states are accepting
1
.table i o CS ->NS
0 0 st0 st0
1 1 st0 st1
0 0 st1 st1
1 1 st1 st2
...
0 0 st31 st31
1 1 st31 st32
0 0 st32 st32
1 1 st32 st0
.end
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