Hardware Reference
In-Depth Information
Fig. 5.6
Machine M
B
for Problem
5.1
Present
Next
Input
state
state
Output
0
a
c
1
1
a
b
0
0
b
a
0
1
b
d
1
0
c
d
0
1
c
b
1
0
d
b
1
1
d
c
0
a
b
1/1
1/1
0/0
0/0
0/0
0/1
2
2
1
1
0/1
0/1
1/0
1/0
1/1
1/1
3
3
Fig. 5.7
Components (
a
) M
A
and (
b
) M
B
of series topology M
A
!
M
B
of Problem
5.2
information-lossless and state-reduced, and so Devadas' and Rho's procedures find
no sequential output don't cares for M
A
. Let the output value
u
i
be associated to the
edge e
i
of M
A
,sothat.
u
1
;
u
2
;
u
3
;
u
4
;
u
5
;
u
6
/ denotes an assignment of output values
to M
A
. E.g., in Fig.
5.7
aitis:e
1
D
1
0=0
2;
u
1
D
0; e
2
D
2
1=1
!
!
2;
u
2
D
1;
0=0
!
1=1
!
1=0
!
e
3
D
2
2;
u
3
D
0; e
4
D
1
3;
u
4
D
1; e
5
D
3
3;
u
5
D
0;
0=1
!
3;
u
6
D
1. Then one can verify that each of the following assignments
preserves the behavior M
A
!
M
B
:
e
6
D
3
8
<
.0;1;0;1;0;1/
.0;1;0;0;1;0/
.1;0;1;0;1;0/
.1;0;1;1;0;1/
.
u
1
;
u
2
;
u
3
;
u
4
;
u
5
;
u
6
/
D
:
Notice that the states reachable in M
A
change according to the output function of
M
A
.
(a) Find out what is
best
assignment with respect to the final implementation of M
A
measured by the number of states and/or its logic cost.
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