Digital Signal Processing Reference
In-Depth Information
^
d
i
^
d
i
Fig. 2.21
DPCM
communication system
with error suppressor
d
i
Z
Quantizer
i
∑
∑
Z
i
-
Z
i
−1
-
ˆ
Z
i
Z
−1
∑
Z
i
−1
Z
−1
Receiver
Transmitter
feedback circuit has been added to the transmitter side. The feedback circuit is basi-
cally same as the receiver circuit. Now let us analyze the transmitter. Here the block
Z
−
1
signifies 1 unit delay (delay by an amount of
T
S
).
At
i
th instant
Z
i
−
1
and
d
i
+
d
i
=
Z
i
−
Z
i
−
1
=
Z
i
(2.30)
Also,
d
i
=
d
i
+
e
q
i
(2.31)
For the 1st sample, i.e. for i
=
1,
d
1
=
d
1
+
e
q
1
So,
Z
1
=
d
1
+
Z
0
(2.32)
=
d
1
+
Z
0
+
e
q
1
=
Z
1
+
e
q
1
For i
=
2, from Eq. (
2.31
) we get
d
2
=
d
2
+
e
q
2
(2.33)
Now,
d
2
+
Z
1
=
Z
2
So,
Z
2
=
d
2
+
e
q
2
+
Z
1
(2.34)
=
Z
2
+
e
q
2
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