Error Control Coding - Digital Communication: Principles and System Modelling - page 191

2. The notation n in the three-tuple notation is exactly the number of output
sequences in the encoder.
3. The notation k is the number of input sequences (and hence, the encoder consists
of k shift registers).
4. The value of m signifies the maximum length of the k shift registers (i.e., if the
number of stages of the jth shift register is K j , then m = max

1

K j ).

≤ j ≤ k

j = 1

k

5. K = K j is the total memory in the encoder (K is sometimes called the overall

constraint lengths, popularly expressed as m+1).

Fig. 9.3 Encoder for binary (2,1,2) convolutional code

In the above two register encoder model (Fig. 9.3 ), at each count of clock pulse,
two bits are taken out in parallel and then converted to serial output. The outputs of
the registers are fed to two different MOD-2 addition modules through two different
connections.

Fig. 9.4 Encoder for binary
(3,2,2) convolutional code

The next configuration (Fig. 9.4 ) takes two bits as inputs t a time and through 2
shift registers and MOD-2 addition configuration responds in two terminals in the
pre-final stage. The rule of encoding must be uniform for both the cases.

9.4.1.1 Operation

Coming to the principle of operation of the convolutional encoder, we can view
the entire process of encoding as a Linear Time Invariant (LTI) system. At each
instance, the input bits are processed selectively through MOD-2 counter. According
to Fig. 9.5 , v 1 bit stream is generated as the output of the upper XOR gate. All
the three inputs of that XOR gates is actively connected. Therefore, the connection