Spread Spectrum Modulation - Digital Communication: Principles and System Modelling - page 142

7.3.2 Generation of PN Sequence

In Fig. 7.3 a, an m-bit length serial in parallel out shift register is shown [ 2 , 5 ].
From all the flip-flops of the shift register, outputs are fed to one logic circuit with
one switch to each. The output of the logic circuit is again fed to the input of the
primary (left most) flip-flop. This arrangement is called as feedback shift register
arrangement.

Fig. 7.3 ( a ) Feed back shift
Register. ( b ) PN sequence
generator

Logic

1 2 3 m o/p seq

Cl k

MOD-2

s 0 s 1 s 2 s 3

o/p seq

1 2 3

Clk

PN sequence can be easily generated by using the feedback register arrangement.
Here I have considered 3 flip-flops with outputs s 1 , s 2 , s 3 . Therefore the length of the
shift register is m 3. The output of the entire system is s 3 . Its also can be said from

Fig. 7.3 b that, after a clock pulse is encountered, s 2

=

s 3 .
The entire system state table is as follows, taking initial contents of the shift register
'1111':
From Table 7.1 , the shift register configuration shown in the Fig. 7.3 b, is gen-
erating a sequence '1110100' followed by the same sequence again and again,

= s 1 , s 3 = s 2 , s 1 = s 1 ⊕

Table 7.1 State table for PN sequence generation
Intermediate states

Clock
pulse no.

Output

S 1 S 2 S 3

1 1 1 1 1

2 0 1 1 1

3 1 0 1 1

4 0 1 0 0

5 0 0 1 1

6 1 0 0 0

7 1 1 0 0

8 1 1 1 1