The Implementing and Researching of BIT in Airborne Computer - Advanced Research on Computer Education, Simulation and Modeling - page 195

n

n n

P ( K )

P ( K ) P ( K ) P ( K ) = (5)

…

m

1 2

n: the repeat test number of single test point.
In formula (5 , for

KP . But the more lager the
repeat test number is, the test software is more complex and the time expended on test is
longer. In this paper, n assigned 3. The flow chart of the BIT system in the airborn
computer is show as follow:

P ( K ) P ( K )

n

( )

<1, <<

m m m

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)RUELGRWKHUPLVVLRQ

%,7DFWLRQ

,QSXWGDWD

1

'DWDULJKW

<

5LJKWWLPH ˇ

7HVWWLPH

WLPH

<

1

5LJKWWLPH !

<

0 ˇ

1H[WFKDQQHO
WHVW

1

0! ˙
<
%,7ULJKW
HQG

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Fig. 1. The flow chart of the BIT system in the airborn computer

3 The BIT Method and Fault Isolation of Partial System

BIT test need special hardware, the test circuit for different partial system test is
different. The basic test need executed in the airborn computer include: digital I/0
channel test, A/D D/A channel test, serial interface test, and the test methods is
discussed as follow.

3.1 Digital I/O Channel Test and Fault Isolation

The airborn computer digital I/O channel is used for digital signal input and output.
Generally there are many digital I/O channel in airborn computer. If each channel test
by special test circuit, the BIT system would be complex and big size, and the reliability