Hard Partitioning: Dynamic Domains - Oracle Solaris 10 System Virtualization Essentials - page 54

Table 2.2 Memory Access Latency

M4000 M5000 M8000 M9000-32 M9000-64

Minimum Latency 245 ns 312 ns 342 ns 387 ns 437 ns

Maximum Latency 245 ns 353 ns 402 ns 464 ns 532 ns

Ratio 1 1.13 1.18 1.20 1.22

Minimum latency reflects the amount of time necessary to access the nearest
memory, and maximum latency reflects the amount of time necessary to access
the farthest memory. As the system size grows, minimum latency increases due
to the cache coherency requirements of the system bus. This factor explains the
recommendation to choose adjacent boards for a domain.
In the event the system boards are placed in quad mode, the addressing from
the XBU is handed off to the SC ASIC. The SC ASICs on each system board are
responsible for the data pathway access, and the SC further restricts the data
pathways. This constraint applies to other XSBs on the same board, as well as
addressing from other XSBs on other boards, with data passed via the XBU.

2.2.2 Domain Combinations
Dynamic Domains offer flexible configuration and assignment of resources. A
key requirement of any virtualization solution is the ability to assign the cor-
rect resources where they are needed. In the previous examples, I/O was always
shown alongside the CPU/memory board. While the IOU will always require the
corresponding CMU board, the presence of a CMU board does not require the IOU
board. Thus it possible to build CPU-heavy and memory-heavy domains, especially
true when specifying CMU boards as floaters, either in Uni-XSB mode or in Quad-
XSB mode.
The remainder of this section considers several combinations of system board
XSB settings of the M4000 and M5000 and possible domain configurations.
Figure 2.9, top left, is the simple case: The system board is in Uni-XSB mode and
supports a single domain. As mentioned earlier, the M4000/M5000 system board
can support two and four domains, respectively, and the top right and bottom
left diagrams in Figure 2.9 show this in different ways. Although both diagrams
depict the system board in Quad-XSB mode, each quad is assigned differently. The
diagram on the top right shows XSB00-0 as Domain 1 and XSB00-1 as Domain
2; XSB00-3 and XSB00-4 are not assigned, but rather are floater XSB units. The
diagram on the bottom left, in contrast, shows all four quads in use: XSB00-0
and XSB00-3 are in Domain 1 and XSB00-1 and XSB00-2 are in Domain 2. The
bottom right diagram shows the possibility of no IOU installed, yet the CPU and