Information Technology Reference
In-Depth Information
(“inflate the balloon”). This action reduces the number of pages the guest OS can
allocate to applications, which reduces the size of its working set and its contribu-
tion to memory pressure on the hypervisor.
Another approach is exemplified by Solaris Containers, which use a single re-
source manager for a Solaris instance with many virtual environments. Because
only one memory manager is present, the problem is neatly and elegantly
side-stepped.
Finally, the economics of memory prices now make it feasible to simply not
oversubscribe memory as was necessary in the VM/370's day. This practice is used
with Logical Domains, which allocate to each guest an amount of real memory
that matches the guest's virtual memory size. While this tactic constrains the
number of domains that can run at any moment in time, it eliminates this entire
complex category of problem. Instead, Logical Domains keep all MMU logic in the
hypervisor.
Memory Management: Multiple Address Spaces
Another expensive situation arose in trying to efficiently provide virtual memories
to guest operating systems that themselves provide virtual memories. The dif-
ficulty in this case is not the ability to provide enough RAM to support memory
requirements for each guest, but rather the task of efficiently translating their
virtual addresses to the real RAM addresses in which they reside.
This problem can be explained by describing how most processors translate
virtual addresses into real ones. One common scheme divides virtual memory
addresses used by processes into segment, page, and offset components. The seg-
ment number is used as an index into an array (the segment table) of virtual
address segments owned by the process, to point to the pages belonging to that
segment. The page number is used as an index into this table, and points to an
entry containing the address of the physical page in RAM containing the virtual
address page. Finally, the offset part of the virtual address is added to the page
address, producing the real memory address corresponding to the virtual address.
If this scheme was implemented literally as described above, every applica-
tion reference to memory would require at least two more memory references.
Requiring three memory references for every user memory reference would im-
pose an intolerable overhead. Instead, most processors cache recently translated
virtual page addresses in a translation look-aside buffer (TLB), a fast associative
memory that can be probed for a page table entry (PTE) with a matching segment
and page address in a single cycle. (The SPARC name for this associative table is
the Page Descriptor Cache [PDC], but this appendix uses the generic term.)
If a segment and page address has been recently used, it will appear in the TLB
and the matching real-memory address will be used. If the entry is not present,
Search WWH ::
Custom Search