Realisation of Digital Filters - Digital Signal Processing: A Practitioner's Approach - page 119

Table 5.2 Synthesis report for the FPGA implementation

Resources Used Avail Utilisation

Input/output 32 140 22.86

Global buffers 0 16 0.00

Function generators 451 2816 16.02

CLB slices 226 1408 16.05

DFFs or latches 0 3236 0.00

Block RAMs 0 12 0.00

Block multiplier 4 12 33.33

Total FPGA 713 7640 9.33

peak (Figure 5.14(b)), but this is only due to the lower resolution (4 bits). The
synthesis report in Table 5.2 gives the silicon utilisation. CLBs are configurable
logic blocks and DFFs are delay flip-flops.

5.9 Summary
In this chapter we described various hardware elements that are frequently used to
convert the given analogue signal into digital form. We implemented a second-order
BPF in SIMULINK and in fixed-point hardware then compared the results. We
looked at a hardware realisation scheme that led us to consider pipelining and its
associated problems. We gave an in-depth discussion on various methods of
pipelining FIR and IIR filters. Then we looked at a complex algorithm for
estimating frequency based on time series data and implemented on the
DSP5630X using C. To implement this algorithm using FPGAs, we chose a design
using FIR filters.

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