Realisation of Digital Filters - Digital Signal Processing: A Practitioner's Approach - page 106

original filter (5.4) as a set of two independent difference equations with minimum
delays gives an important clue about the realisation. Equation (5.5) needs two
multiplications and two additions, and the multiplications can be carried out
simultaneously. Figure 5.6 shows a SIMULINK 1 implementation of the filter.
There are many third-party vendors providing code generation packages on your
chosen processors.

5.4.1 Fixed-Point Implementation
We have directly implemented a filter given as H ð z Þ into floating-point hardware.
This may not always be the case. For greater speed and for other reasons such as
cost and maintainability, the fixed-point implementation is still a very useful

architecture.
This needs a different approach. As a first step, we need to convert the filter
coefficients into rational numbers (of the form p = q). The denominator will be a
number of the form 2 N , where N is an integer:

w k 1 w k 2 þ u k ;

2 16
256

411
256

252
256

w k ¼

ð 5 : 7 Þ

x k ¼ 256w k 256w k 2 :

In this numerical example we have N ¼ 8. This means the input is first required
to be shifted left 16 places for making a multiplication with 2 16 . It means that we
need a 24-bit adder if the input is an 8-bit A/D converter. On making fixed-point
multiplication and addition, we shift right 8 times for dividing by 256 to generate
w k . The fixed-point implementation is shown in Figure 5.7. Each register provides
the delay and the registers are clocked with a minimum period (t c ) equal to the time
taken for one multiplication (t ) and one addition (t þ ), so t c t þ t þ . It means that
the output of the register settles only after period t d ¼ t s þ t þ t þ where t s is the
register set-up time. We have used two registers r 1 (input r i 1 and output r 1 ) and r 2 in
the above hardware and the information is sequenced as follows (Figure 5.7).

r i 1 (¼ ½ r 2 þð 2 16 Þ u 2 8

Settling time ¼ t þ ; ð 5 : 8 Þ

r i 2 (¼ 252r 1 þ 411r i 1

Settling time ¼ t þ t þ þ t ; ð 5 : 9 Þ

r i 1 ! r 1 r i 2 ! r 2 Clocking of registers :

Clocking of the registers can be done only after the combinatorial circuit outputs
connected to the inputs of the two registers (r i 1 and r i 2 ) settle. Figure 5.8 compares
the fixed-point filter with the floating-point filter.

1

A software package from MathWorks of the US.