Realisation of Digital Filters - Digital Signal Processing: A Practitioner's Approach - page 104

Figure 5.4 Flash analogue-to-digital converter

where n is the desired conversion width. Equation (5.2) is shown in Figure 5.4
implemented in analogue form. The weight w i ¼ð 2 i 1 Þ 2 n is obtained using a

resistor in a potential divider formation. Comparators are high slew rate operational
amplifiers specifically designed to meet

=

the speed requirements. A vector

b ¼½ b 1 ; b n 1 is generated and encoded in the desired format using

a logic function providing the digital output as b x k c .
Notice this scheme has complex hardware. There are many methods available in
the literature [4] to obtain higher-order conversions using 3-bit flash converters.

b 2 ; ; b n 2 ;

5.3.3 Sigma-Delta Converters
In sigma-delta converters (Figure 5.5) the signal y ð t Þ is compared with a binary
signal b k which indicates whether the signal y ð t Þ is in the top half or the bottom half
of the conversion range:

z ð t Þ¼ ð e ð t Þ dt is obtained

e ð t Þ¼ y ð t Þ b k and : ð 5 : 3 Þ

The signal z ð t Þ is passed through a hard limiter generating a bitstream b k .

Figure 5.5 Sigma-delta converter