Electro-Optics - Applied Optics Fundamentals and Device Applications - page 42

derating of the current handling capability of the pins. Any small difference
in contact resistance will significantly unbalance the current flows.
2.5.5 Large-Scale Integration Challenges
Many problems and issues remain to be resolved in the packaging and gen-
eral usage of large-scale integration chips. The first of these issues concerns
high-level interconnections among LSI components and devices. Although
the development of LSI technology has been rapidly progressing, the only
major interconnection issue that has been addressed has been at the chip-to-
chip level. It is felt that a critical path in the incorporation of LSI components
into various designs will be interfacing at the backplane and intercabinet lev-
els. This will be particularly true for the interface speeds of LSI components.
The second issue is the actual insertion of LSI components into exist-
ing systems and the incorporation of these components into new product
designs. The new problems of LSI electrical interconnects stem from two
sources. First is the necessity to transmit high-speed data and clock signals
over distances that are incompatible with the drive capabilities of the chips.
Second is the lack of control of clock offsets between widely separated func-
tional entities.
A prime consideration affecting communication between chips is the drive
capabilities of the chips themselves. Additionally, these limitations do not
allow the direct driving of any currently available optical sources. Analysis
suggests that the critical length separating lumped element and transmission
line considerations is on the order of 10 cm. This was obtained from calcula-
tions using a rise time of 7 ns as representative of typical 25 MHz chip signals.
A hierarchical approach to system implementation is envisioned wherein
chips containing closely interacting functions or groups of functions are assem-
bled in close spatial proximity as higher function modules. Combinations of
superchip modules and line drivers should suffice for structuring circuits at
the board level. The design goal is to minimize the number and length of
high-speed transmission paths. Experience indicates the number of inter-
connections between assemblies decreases as one moves up through higher
level assemblies. In the case of fewer high-speed channels traversing greater
distances, higher power transmitters and more sophisticated receivers can
be tolerated. Also, the requirement for synchronous clocking diminishes at
higher assembly levels. At certain levels in signal processors, we move from
intra- to intercomputer situations. These widely separated elements need to
communicate over high-speed data connections—data connections that are
impracticable given the chip drive capabilities.
2.5.6 Advantages of Optical Interconnects
There are a number of limitations of conventional interconnects that
can be alleviated through the use of optical interconnects. The general