Integrated Optics - Applied Optics Fundamentals and Device Applications - page 267

5. Optimize the design and do a rough circuit layout.

6. Calculate the device parasitics and incorporate them into the design.

7. Re-optimize the design over temperature and process variations.

8. Run the circuit through a design rule checker to ensure that none of
the basic layout rules have been violated.

9. Conduct a layout review at the foundry.

Computer analysis and synthesis software has been developed to meet the
needs of the microwave designer by a number of sources. Companies are
now providing the software packages that enable the engineer to design cir-
cuitry, perform analysis and optimization functions, and transfer layouts. In
addition, they furnish the user with foundry libraries to enable simulation of
a MMIC implementation of the user's circuitry. Figure 5.30 [97] indicates the
range of CAE/CAD software available from one manufacturer and demon-
strates how this software fits into a systematic design flow.
After the design sequence is completed the foundry is generally assigned
the task of generating the masks required to produce the finished wafer.
After the wafer is produced, the foundry test facility is able to run tests on
the various dies on the wafer according to test points that have been made
available by the designer. A typical test setup [98] for wafer testing is shown
in Figure 5.31.

Synthesis
E-syn

Schematic
capture

Structures
linecalc

Simulators and libraries

Harmonic balance
simulators

Touchstone µw spice

Foundry libraries and active device models

Mask layout

Micad Full custom IC layout

Design rule checking
Mask manufacturing
Fabrication
Test
Anacat-touchstone

Cell libraries

MMIC

FIGURE 5.30
EESOF product suite. (After Parrish, P. of EESOF, Computer-aided engineering in GaAs mono-
lithic technology, Monolithic Technology , October 1987.)