Digital Signal Processing Reference
In-Depth Information
pattern of nonuniform distances between them. It is relatively difficult to ensure
in this case that all generated sampling pulses are placed exactly on the time grid.
Hence there are imperfections in the generation process, which are observed as
jitter of the sampling pulse generation instants.
It seems that the best approach to the generation of sampling pulse trains is to
combine both techniques. This method is illustrated later in Figure 11.3 where a
block diagram of a generator implementing this method is shown. Such a com-
bination of these techniques makes it possible to use moderate clock frequencies
and the quantity of the used delay elements is reduced to a relatively small number.
As a result, the generator shown in Figure 11.3 generates sampling pulses with
high precision while the jitter does not exceed a few picoseconds. To form sam-
pling pulses according to a predetermined nonuniform pattern, the pulse forming
process is based on controllable division of the clock frequency followed by con-
trollable introduction of time delays. The generator of pseudo-random numbers
provides the code for digital control of this process. This is discussed in more
detail in Chapter 11.
To continue the illustration of this example, some figures characterizing a
particular generator are given. The periodic clock pulses were generated at the
rate of 669.3266 MHz. The clock frequency was divided by a random integer
ranging from 9 to 16. Then the output pulses were expanded in width (up to
approximately 5 ns). An adjustable delay line and a high-speed multiplexer were
used to implement a single-bit controllable delay block. As a result, the inter-
vals between the generated sampling pulses at the output of the generator were
pseudo-randomly varied from 13.447 to 24.652 ns with the smallest time digit
equal to 747 ps. This generator is adapted for joint operation over a wide range of
ADCs with the maximum sampling rate over 80 MS/s and a broad analog band-
width. Although in the particular considered case the mean sampling rate is only
53.546 MS/s, the equivalent sampling rate is much higher, providing for digi-
tal alias-free signal processing in the bandwidth up to 669.3 MHz. It should be
emphasized that the introduced tight control of the sampling pulse jitter made
it possible to achieve a bandwidth free from the spurious frequencies due to
sampling imperfections.
Bibliography
Artjuhs, J. and Bilinskis, I. (2006) Method and apparatus for alias suppressed digitizing of high frequency
analog signals. EP 1 330 036 B1, European Patent Specification, Bulletin 2006/26, 28.06.2006.
Artyukh, Yu., Bilinskis, I. and Vedin, V. (1999) Hardware core of the family of digital RF signal PC-based
analyzers. In Proceedings of the 1999 International Workshop on
Sampling Theory and Application
,
Loen, Norway, 11-14 August 1999, pp. 177-9.
